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jtwn 06-04-2005 13:23

L2 cache question
 
When does the 1mb L2 cache make a noticeable difference over 512k?

I've read that a 3800+ will act like an FX-53, until the extra cache is needed...what would use it?

TheBlueRaja 06-04-2005 14:27

Re: L2 cache question
 
Cache is small high speed memory usually Static RAM (SRAM) that contains the most recently accessed pieces of main memory.

In todayââ‚ÆšÂ¬ÃƒÂ¢Ã¢â‚¬Å¾Ã‚¢s systems , the time it takes to bring an instruction (or piece of data) into the processor is very long when compared to the time to execute the instruction. Therefore a bottle neck forms at the input to the processor. Cache memory helps by decreasing the time it takes to move information to and from the processor. Therefore cache memory allows small portions of main memory to be accessed 3 to 4 times faster than DRAM (main memory).

The theory that explains this performance is called †œLocality of Reference.âââ€Å ¡Ã‚¬Ã‚ The concept is that at any given time the processor will be accessing memory in a small or localized region of memory. The
cache loads this region allowing the processor to access the memory region faster.

(Yes - i got this somewhere else :D )

zing_deleted 06-04-2005 14:51

Re: L2 cache question
 
Damn i was mighty impressed till i read the last bit lol lol lol

TheBlueRaja 06-04-2005 14:53

Re: L2 cache question
 
Yeah i was going to blag it to impress until i realised that after i spouted †œLocality of Reference.âââ€Å ¡Ã‚¬Ã‚ i wouldnt have a chance of getting away with it. :D

zing_deleted 06-04-2005 14:54

Re: L2 cache question
 
Lmao

Matth 06-04-2005 17:55

Re: L2 cache question
 
A loop that is a few bytes smaller than the cache will execute at cache speed.

A loop that is a few bytes larger than the cache, may end up executing entirely at main RAM speed, as both the common rules ... LRU and LFU will both let what's most needed slip away.

Actually, another rule for cache line discarding would work better - RANDOM.

The other problem with caches - their own speed (in the shape of increased latency) tends to fall if the size of cache is increased wiithout improving the cache architecture.

I did learn about tags, dirty bits and all that.


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